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PMC-CTR64 Counter / Timer
with TTL Level I/O

The PMC-CTR64 is a TTL level compatible I/O PMC mezzanine module providing 8 x 16 bits Counter / Timers and 32 bits of general purpose I/O.  A PLX PCI9030 device controls the PCI bus and a Xilinx SpartanXL is used to provide the on-board functionality.  The 32 external I/O lines are software configurable as inputs or outputs and are routed to the front panel SCSI-2 style connector and to the P4 connector for rear I/O interfacing together with the 24 input and 8outpus for the counter / timers.

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Block Diagram

 

PCI Features

The PMC-CTR32 uses a PLX PCI9030 PCI interface to a 16-bit local bus on-board. The general features of the PCI9030 are:

  • PCI Local Bus Specification V2.2-compliant 32-bit, 33 MHz Bus Target Interface Device enabling PCI Burst Transfers up to 132 MB/s.
  • PCI Bus Power Management Interface Specification V1.1 compliant.
  • PCI Local Bus Specification V2.2 Vital Product Data (VPD) configuration support.
  • PCI Target Programmable Burst Management.
  • PCI Target Read Ahead mode.
  • PCI Target Delayed Read mode.
  • PCI Target Delayed Write mode.
  • Programmable Interrupt Generator/Controller.
  • Two programmable FIFOS for zero wait state burst operation.
  • Flexible Local Bus provides 32-bit Multiplexed or Non-Multiplexed Protocol for 8, 16, or 32-bit Peripheral and Memory devices.
  • Serial EEPROM interface.
  • Nine programmable General Purpose I/O (GPIOS).
  • Five programmable Local Address spaces.
  • Four programmable independent chip selects.
  • Programmable Local Bus wait states.
  • Programmable Local Read pre-fetch mechanism.
  • Local Bus can run asynchronously to the PCI Bus.
  • Two programmable Local-to-PCI interrupts.
  • Endian Byte Swapping.

Main Logic

The PMC-CTR32 uses a Xilinx SpartanXL FPGA connected to the 16-bit local bus to provide the on-board logic functions as described below.

General Purpose Input Register

A 32-bit register containing a latched version of the general purpose I/O pins on the logic device. The signals are latched by the 33MHz PCI clock.

Counter / Timer Output Register

An 8 bit register containing the levels of the output pins on the logic device.

Counter / Timer Clock Register

An 8bit clock register containing the level of the timer / counter clock input pins on the logic device.

Counter / Timer Gate Register

An 8 bit register containing the level of the gate input pins on the logic device.

Counter / Timer Direction Register

An 8-bit register containing the level of the direction input pins on the logic device.

General Purpose Output Register

A 32-bit register whose contents are output to valid general purpose output pins.

Counter / Timer Status Register

An 8 bit register where each bit indicates that the counter / timer output is active.

Counter / Timer Output Control Register

An 8 bit register where each bit is used to select the polarity of the counter /timer output.

Counter / Timer Interrupt Enable Register

An 8 bit register where each bit is used to enable the interrupt for the corresponding counter / timer.

Counter / Timer Clock source Register

An 8 bit register where each bit is used to select internal or external clock for the counter / timer source.

Counter / Timer Direction Register

An 8 bit register where each bit correspond to a group of 8 I/O bits.

Function Register

An 8 bit register which contains the low byte of the PCI Subsystem Device ID - used to determine the type of board fitted from the PMC-DIO and PMC-CTR families.

Control and Status Register

A 16 bit register used to control and monitor the status of the following functions:

  • Watchdog Interrupt Control
  • Global Output Control
  • Watchdog Enable Control
  • Watchdog Status
  • Counter / Timer Clock Selection
  • Lock Inputs Control.

Watchdog Trigger Register

An 8 bit register in which bit 0 must be written alternately 0 and 1 within 25% of the watchdog timer period.

Watchdog Timer Register

An 8 bit register defining the watchdog timer period: 125ms, 250ms, 500ms, 1sec or 2 sec.

Watchdog Status Register

An 8 bit register which indicates that the watchdog has timed out.

Counter / Timer Value Register

A 16-bit register for each counter / timer which can be used to set the count value and read to return the current count value.

Counter / Timer Operation

On the rising edge of the Counter / Timer CLOCK the state of the DIRECTION and GATE inputs are latched. The counter is updated dependent on the DIRECTION and GATE values.

I/O Interface

The 64-bits of I/O are connected to the outside world via 74ABT16245A buffers.  These buffers have 32/64mA source/sink capabilities respectively.

93CS56 EEPROM

The PMC-CTR64 is fitted with a 93CS56 EEPROM which is supplied pre-programmed by BVM. The contents of this EEPROM are read by the PCI9030 on coming out of reset and are used to set up the control registers after reset, configuring the PCI interface configuration, PCI Device/Vendor ID's & various other board specific parameters.

18V256 EEPROM

The PMC-CTR64 is fitted with a 18V256 EEPROM, which is supplied pre-programmed by BVM. The contents of this EEPROM are read by the SpartanXL FPGA on power up and are used to initialise the logic functions in the FPGA.

Specification

On-Board Functions

PCI9030 PCI Interface

PCI 2.2 compliant 32-bit, 33-MHz Bus Target Interface Device
PCI Target Delayed Read mode disabled
PCI Target Read Ahead mode disabled
PCI Target Delayed Write mode disabled
Programmable Interrupt Generator
Local Bus provides 32-bit non-multiplexed 16-bit peripheral access
Local Bus zero wait state
Programmable Local-to-PCI interrupt

SpartanXL FPGA

General Purpose Input Register
Counter / Timer Clock Register
Counter / Timer Output Register
Counter / Timer Gate Register
Counter / Timer Direction Register
General Purpose Output Register
Counter / Timer Status Register
Counter / Timer Output Control Register
Counter / Timer Interrupt Enable Register
Counter / Timer Clock Source Register
Direction Register
Function Register
Status and Control Register
Watchdog Trigger Register
Watchdog Timer Register
Watchdog Status Register
8 x Counter / Timer registers

Local Clocks

    32.768KHz timer clock

Board Configuration

Links
Pull-up enables
Common selection

EEPROM
PCI Configuration
FPGA Configuration

I/O Interface
64-bits TTL compatible I/O
I/O direction byte selectable
global output enable
74ABT16245A buffers
32mA source capacity
64mA sink capacity
Re-settable fuse protected at 2.5A

Counter / Timer Functions
8 x 16-bit counter / timers
External or internal clock input
Internal clock frequency select
External Gate input
External Direction input
External output on count rollover
Interrupt on count rollover

PMC Interface
Bus Interface: PCI 2.2 compliant
Bus Width: 32-bit
Bus Speed: 33MHz
Data Transfer: PCI 2.2 Bus Target
Interrupts: PCI INT #A
Memory Address: BIOS assigned

Operating Environment

Dimensions: 74.0mm x 149.0mm (single PMC size)
Power: +3.3V 215mA typical +5V 0mA typical, excluding external requirements
Environmental: 0 to 70 C, 95% humidity non-condensing (extended range to order)

 
BVM Limited can be contacted by Telephone +44 (0)1489 780144  Fax +44 (0)1489 783589
or email sales@bvmltd.co.uk
Copyright 1998-2003 BVM Limited. All rights reserved. All Trademarks acknowledged